What Is CyberWorkBench (CWB)?

• CWB is a C-based design and verification platform for ASIC and FPGA design. It is an ESL-synthesis product.
  
  
• CWB is the most mature C-based design tool in the market. The first tape out of a chip using CWB was in 1993.

What Does CyberWorkBench Do?

• CWB inputs behavioral ANSI-C or SystemC and synthesizes high quality RTL (VHDL or Verilog).
  
  
• CWB can synthesize ANY digital application (whether control or data dominated).
  
  
• CWB provides full chip design capabilities in order to allow entire chips to be designed in C (e.g. bus interface generator, top module generator, behavioral model generator)
  
  
• With CWB, designs can also be fully verified to the behavorial C-code (formal verification, source code debugger, behavioral and cycle accurate simulators). There is no need for RTL verification anymore, although we provide RTL verification tools and interfaces to third party EDA vendor tools.
  
  
• CWB provides automatic design space exploration while automatically generating area vs. performance trade-off graph.
  
  
• CWB provide a Behavioral IP library with fully parameterizable functions (filters, arithmetic operations, encryption algorithms, etc.)

Why Did NEC Create CyberWorkBench?

• CWB was original developed as an in-house tool for NEC Electronics in order to increase productivity and reduce time to market.

What Are The Benefits of Using CyberWorkBench?

• CWB facilitates efficient the design of VLSI circuits.
  
  
• CWB enables better communication between software and hardware engineers. Software algorithms that have to be implemented in HW are getting increasingly complicated and hardware designers sometimes have a hard time understanding these algorithms (e.g. encryption algorithms).
  
  
• CWB drastically improves time to market through increased design productivity (fast architectural exploration and earlier, more productive verification at the C code).
  
  
• CWB provides for code size reduction, leading to fewer bugs and being easier to debug.
  
  
• CWB enables higher source code re-usability.
  
  
• CWB enables design space exploration. Writing a single design in C, CWB can automatically generate different HW architectures with different area, performance, power trade-offs (in RTL each architecture would have to be manually created).

How is CyberWorkBench Better Than Other Competitive Products?

• CWB consistently achieves smaller and faster designs.  This is as a result of the long history of CWB, with all the optimizations built in.
  
  
• CWB is more complete. It consists of over 10 different tools (apart from the main synthesis engine) that allows the verification to the behavorial C, RT-level, hardware software co-simulation, etc.
  
  
• CWB can target both FPGAs and ASIC design styles.

How Can I Learn More About CyberWorkBench?

• Complete the short form below to receive your FREE report or schedule a private demo
  
  
• Or call 408-735-7205.
  
  
• CWB is available in North America through EDATechForce.